View MB95F583HWQN-G-JNERE1_7011593.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright?2010 fujitsu semicondu ctor limited all rights reserved 2010.12 fujitsu semiconductor data sheet for the information for microcontroller supports, see the following website. http://edevice.fujitsu .com/micom/en-support/ 8-bit microcontrollers cmos new-8fx mb95560h/570h/580h series mb95f562h/f562k/f5 63h/f563k/f564h/f564k mb95f572h/f572k/f5 73h/f573k/f574h/f574k mb95f582h/f582k/f5 83h/f583k/f584h/f584k description mb95560h/570h/580h is a series of general-purpose, si ngle-chip microcontrollers. in addition to a compact instruction set, the microcontrollers of these series contain a variety of peripheral resources. features ?new-8fx cpu core instruction set optimized for controllers ? multiplication and division instructions ? 16-bit arithmetic operations ? bit test branch instructions ? bit manipulation instructions, etc. ? clock ? selectable main clock source main oscillation clock (up to 16.25 mhz, maximum machine clock frequency: 8.125 mhz) external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) main cr clock (4 mhz 2%) the main cr clock frequency becomes 8 mhz when the pll multiplier is 2. the main cr clock frequency becomes 10 mhz when the pll multiplier is 2.5. the main cr clock frequency becomes 12 mhz when the pll multiplier is 3. the main cr clock frequency becomes 16 mhz when the pll multiplier is 4. ? selectable subclock source sub-oscillation clock (32.768 khz) external clock (32.768 khz) sub-cr clock (typ: 100 khz, min: 50 khz, max: 150 khz) ?timer ? 8/16-bit composite timer 2 channels ? time-base timer 1 channel ? watch prescaler 1 channel ? lin-uart (available only on mb95f562h/f562k /f563h/f563k/f564h/f564k/f582h/f582k/f583h/ f583k/f584h/f584k) ? full duplex double buffer ? capable of clock-synchronized serial data trans fer and clock-asynchronized serial data transfer (continued) ds702-00003-1v0-e
mb95560h/570h/580h series 2 ds702-00003-1v0-e (continued) ? external interrupt ? interrupt by edge detection (rising edge, falling edge, and both edges can be selected) ? can be used to wake up the device from different low power consumption (standby) modes ? 8/10-bit a/d converter ? 8-bit or 10-bit resolution can be selected. ? low power consumption (standby) modes ? stop mode ? sleep mode ?watch mode ? time-base timer mode ? i/o port ? mb95f562h/f563h/f564h (maximum no. of i/o ports: 16) general-purpose i/o ports (n-ch open drain) : 1 general-purpose i/o ports (cmos i/o) : 15 ? mb95f562k/f563k/f564k (maximum no. of i/o ports: 17) general-purpose i/o ports (n-ch open drain) : 2 general-purpose i/o ports (cmos i/o) : 15 ? mb95f572h/f573h/f574h (maximum no. of i/o ports: 4) general-purpose i/o ports (n-ch open drain) : 1 general-purpose i/o ports (cmos i/o) : 3 ? mb95f572k/f573k/f574k (maximum no. of i/o ports: 5) general-purpose i/o ports (n-ch open drain) : 2 general-purpose i/o ports (cmos i/o) : 3 ? mb95f582h/f583h/f584h (maximum no. of i/o ports: 12) general-purpose i/o ports (n-ch open drain) : 1 general-purpose i/o ports (cmos i/o) : 11 ? mb95f582k/f583k/f584k (maximum no. of i/o ports: 13) general-purpose i/o ports (n-ch open drain) : 2 general-purpose i/o ports (cmos i/o) : 11 ? on-chip debug ? 1-wire serial control ? serial writing supported (asynchronous mode) ? hardware/software watchdog timer ? built-in hardware watchdog timer ? built-in software watchdog timer ? low-voltage detection reset circuit (available only on mb95f562k/f563k/f564k/f572k/f573k/f574k/ f582k/f583k/f584k) ? built-in low-voltage detector ? clock supervisor counter ? built-in clock supervisor counter function ? dual operation flash memory ? the erase/write operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. ? flash memory security function ? protects the content of the flash memory
mb95560h/570h/580h series ds702-00003-1v0-e 3 product line-up ? mb95560h series (continued) part number parameter mb95f562h mb95f563h mb95f564h mb95f562k mb95f563k mb95f564k type flash memory product clock supervisor counter it supervises the main clock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 8 kbyte 12 kbyte 20 kbyte ram capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes low-voltage detection reset no yes reset input dedicated selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general- purpose i/o ? i/o ports (max) : 16 ? cmos i/o : 15 ? n-ch open drain: 1 ? i/o ports (max) : 17 ?cmos i/o :15 ? n-ch open drain: 2 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle - main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be used as the source clock of the hardware watchdog timer. wild register it can be used to replace 3 bytes of data. lin-uart ? a wide range of communication speed can be selected by a dedicated reload timer. ? it has a full duplex double buffer. ? clock-synchronized serial data transfer and clock-asynchronized serial data transfer is en- abled. ? the lin function can be used as a lin master or a lin slave. 8/10-bit a/d converter 6 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 2 channels ? the timer can be configured as an "8-bit timer 2 channels" or a "16-bit timer 1 channel". ? it has built-in timer function, pwc function, pwm function and input capture function. ? count clock: it can be selected from internal clocks (seven types) and external clocks. ? it can output square wave. external interrupt 6 channels ? interrupt by edge detection (the rising edge , falling edge, or both edges can be selected.) ? it can be used to wake up the device from the standby mode. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode).
mb95560h/570h/580h series 4 ds702-00003-1v0-e (continued) part number parameter mb95f562h mb95f563h mb95f564h mb95f562k mb95f563k mb95f564k watch prescaler eight different time intervals can be selected. flash memory ? it supports automatic programming (embedded algorithm) and write/erase/erase-suspend/ erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package lcc-32p-m19 fpt-20p-m09 fpt-20p-m10 number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years
mb95560h/570h/580h series ds702-00003-1v0-e 5 ? mb95570h series part number parameter mb95f572h mb95f573h mb95f574h mb95f572k mb95f573k mb95f574k type flash memory product clock supervisor counter it supervises the main clock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 8 kbyte 12 kbyte 20 kbyte ram capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes low-voltage detection reset no yes reset input dedicated selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general- purpose i/o ? i/o ports (max) : 4 ? cmos i/o : 3 ? n-ch open drain: 1 ? i/o ports (max) : 5 ?cmos i/o :3 ? n-ch open drain: 2 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle - main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be used as the source clock of the hardware watchdog timer. wild register it can be used to replace 3 bytes of data. lin-uart no lin-uart 8/10-bit a/d converter 2 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 1 channel ? the timer can be configured as an "8-bit timer 2 channels" or a "16-bit timer 1 channel". ? it has built-in timer function, pwc function, pwm function and input capture function. ? count clock: it can be selected from internal clocks (seven types) and external clocks. ? it can output square wave. external interrupt 2 channels ? interrupt by edge detection (the rising edge , falling edge, or both edges can be selected.) ? it can be used to wake up the device from standby modes. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode). watch prescaler eight different time intervals can be selected. flash memory ? it supports automatic programming (embedded algorithm) and write/erase/erase-suspend/ erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package fpt-8p-m08 number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years
mb95560h/570h/580h series 6 ds702-00003-1v0-e ? mb95580h series (continued) part number parameter mb95f582h mb95f583h mb95f584h mb95f582k mb95f583k mb95f584k type flash memory product clock supervisor counter it supervises the main clock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 8 kbyte 12 kbyte 20 kbyte ram capacity 240 bytes 496 bytes 496 bytes 240 bytes 496 bytes 496 bytes low-voltage detection reset no yes reset input dedicated selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general- purpose i/o ? i/o ports (max) : 12 ? cmos i/o : 11 ? n-ch open drain: 1 ? i/o ports (max) : 13 ?cmos i/o :11 ? n-ch open drain: 2 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle - main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be used as the source clock of the hardware watchdog timer. wild register it can be used to replace 3 bytes of data. lin-uart ? a wide range of communication speed can be selected by a dedicated reload timer. ? it has a full duplex double buffer. ? clock-synchronized serial data transfer and clock-asynchronized serial data transfer is en- abled. ? the lin function can be used as a lin master or a lin slave. 8/10-bit a/d converter 5 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 1 channel ? the timer can be configured as an "8-bit timer 2 channels" or a "16-bit timer 1 channel". ? it has built-in timer function, pwc function, pwm function and input capture function. ? count clock: it can be selected from internal clocks (seven types) and external clocks. ? it can output square wave. external interrupt 6 channels ? interrupt by edge detection (the rising edge , falling edge, or both edges can be selected.) ? it can be used to wake up the device from standby modes. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode).
mb95560h/570h/580h series ds702-00003-1v0-e 7 (continued) part number parameter mb95f582h mb95f583h mb95f584h mb95f582k mb95f583k mb95f584k watch prescaler eight different time intervals can be selected. flash memory ? it supports automatic programming (embedded algorithm) and write/erase/erase-suspend/ erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory standby mode sleep mode, stop mode, watch mode, time-base timer mode package lcc-32p-m19 fpt-16p-m08 fpt-16p-m23 number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years
mb95560h/570h/580h series 8 ds702-00003-1v0-e packages and corre sponding products ? mb95560h series ? mb95570h series ? mb95580h series o: available x: unavailable part number package mb95f562h mb95f562k mb95f563h mb95f563k mb95f564h mb95f564k lcc-32p-m19oooooo fpt-20p-m09oooooo fpt-20p-m10oooooo fpt-16p-m08xxxxxx fpt-16p-m23xxxxxx fpt-8p-m08xxxxxx part number package mb95f572h mb95f572k mb95f573h mb95f573k mb95f574h mb95f574k lcc-32p-m19xxxxxx fpt-20p-m09xxxxxx fpt-20p-m10xxxxxx fpt-16p-m08xxxxxx fpt-16p-m23xxxxxx fpt-8p-m08oooooo part number package mb95f582h mb95f582k mb95f583h mb95f583k mb95f584h mb95f584k lcc-32p-m19oooooo fpt-20p-m09xxxxxx fpt-20p-m10xxxxxx fpt-16p-m08oooooo fpt-16p-m23oooooo fpt-8p-m08xxxxxx
mb95560h/570h/580h series ds702-00003-1v0-e 9 differences among products and notes on product selection ? current consumption when using the on-chip debug function, take account of the current consumption of flash erase/write. for details of current consumption, see ? electrical characteristics?. ? package for details of information on each package, see ? packages and corresponding products? and ? package dimension?. ? operating voltage the operating voltage varies, depending on whether the on-chip debug function is used or not. for details of the operating voltage, see ? electrical characteristics?. ? on-chip debug function the on-chip debug function requires that v cc , v ss and 1 serial-wire be connected to an evaluation tool. for details of the connection method, refer to ?chapter 21 example of serial programming connection? in the hardware manual of the mb95560h/570h/580h series.
mb95560h/570h/580h series 10 ds702-00003-1v0-e pin assignment (continued) fpt-20p-m09 fpt-20p-m10 (mb95560h s erie s ) p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/ s in/ec0 p0 3 /int0 3 /an0 3 / s ot p02/int02/an02/ s ck p01/an01 p00/an00 p64/ec1 x0/pf0 x1/pf1 v ss x1a/pg2 x0a/pg1 vcc c r s t/pf2 to10/p62 to11/p6 3 (top view) 20 19 1 8 17 16 15 14 1 3 12 11 1 2 3 4 5 6 7 8 9 10 nc nc nc nc nc nc p07/int07 p12/ec0/dbg x1/pf1 x0/pf0 v ss x1a/pg2 x0a/pg1 vcc (top view) lcc- 3 2p-m19 (mb95560h s erie s ) 3 2 3 1 3 0 29 2 8 27 nc 26 nc 25 24 2 3 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/ s in/ec0 p0 3 /int0 3 /an0 3 / s ot 22 21 20 19 p02/int02/an02/ s ck 1 8 p01/an01 17 1 2 3 4 5 6 c7 r s t/pf2 8 to11/p6 3 to10/p62 9 10 nc nc nc 11 12 1 3 nc 14 p00/an00 15 p64/ec1 16 * the n u m b er of usab le pin s i s 20.
mb95560h/570h/580h series ds702-00003-1v0-e 11 (continued) fpt-16p-m0 8 fpt-16p-m2 3 (mb955 8 0h s erie s ) fpt- 8 p-m0 8 (mb95570h s erie s ) p12/ec0/dbg p06/int06/to01 p05/an05/to00 p04/int04/an04/ec0 v ss vcc c r s t/pf2 (top view) 8 7 6 5 1 2 3 4 p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/ s in/ec0 p0 3 /int0 3 /an0 3 / s ot p01/an01 p02/int02/an02/ s ck x0/pf0 x1/pf1 v ss x1a/pg2 x0a/pg1 vcc r s t/pf2 c (top view) 16 15 14 1 3 12 11 10 9 1 2 3 4 5 6 7 8 nc nc nc nc nc nc p07/int07 p12/ec0/dbg x1/pf1 x0/pf0 v ss x1a/pg2 x0a/pg1 vcc (top view) lcc- 3 2p-m19 (mb955 8 0h s erie s ) 3 2 3 1 3 0 29 2 8 27 nc 26 nc 25 24 2 3 p06/int06/to01 p05/int05/an05/to00 p04/int04/an04/ s in/ec0 p0 3 /int0 3 /an0 3 / s ot 22 21 20 19 p02/int02/an02/ s ck 1 8 p01/an01 17 1 2 3 4 5 6 c7 r s t/pf2 8 nc nc 9 10 nc nc nc 11 12 1 3 nc 14 nc 15 nc 16 * the n u m b er of usab le pin s i s 16.
mb95560h/570h/580h series 12 ds702-00003-1v0-e pin functions (mb 95560h series, 32 pins) (continued) pin no. pin name i/o circuit type* function 1 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 2 pf0 b general-purpose i/o port x0 main clock input oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7c ? capacitor connection pin 8 pf2 a general-purpose i/o port rst reset pin dedicated reset pin in mb95f562h/f563h/f564h 9 p63 e general-purpose i/o port high-current pin to11 8/16-bit composite timer ch. 1 output pin 10 p62 e general-purpose i/o port high-current pin to10 8/16-bit composite timer ch. 1 output pin 11 nc ? it is an internally connected pin. always leave it unconnected. 12 nc ? it is an internally connected pin. always leave it unconnected. 13 nc ? it is an internally connected pin. always leave it unconnected. 14 nc ? it is an internally connected pin. always leave it unconnected. 15 p00 d general-purpose i/o port high-current pin an00 a/d converter analog input pin 16 p64 e general-purpose i/o port high-current pin ec1 8/16-bit composite timer ch. 1 clock input pin 17 p01 d general-purpose i/o port high-current pin an01 a/d converter analog input pin 18 p02 d general-purpose i/o port high-current pin int02 external interrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin
mb95560h/570h/580h series ds702-00003-1v0-e 13 (continued) * : for the i/o circuit types, see ? i/o circuit type?. pin no. pin name i/o circuit type* function 19 p03 d general-purpose i/o port high-current pin int03 external interrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin 20 p04 d general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin 21 p05 d general-purpose i/o port high-current pin int05 external interrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 22 p06 e general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 output pin 23 p12 f general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin 24 p07 e general-purpose i/o port high-current pin int07 external interrupt input pin 25 nc ? it is an internally connected pin. always leave it unconnected. 26 nc ? it is an internally connected pin. always leave it unconnected. 27 nc ? it is an internally connected pin. always leave it unconnected. 28 nc ? it is an internally connected pin. always leave it unconnected. 29 nc ? it is an internally connected pin. always leave it unconnected. 30 nc ? it is an internally connected pin. always leave it unconnected. 31 nc ? it is an internally connected pin. always leave it unconnected. 32 nc ? it is an internally connected pin. always leave it unconnected.
mb95560h/570h/580h series 14 ds702-00003-1v0-e pin functions (mb 95560h series, 20 pins) (continued) pin no. pin name i/o circuit type* function 1 pf0 b general-purpose i/o port x0 main clock input oscillation pin 2 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7 c ? capacitor connection pin 8 pf2 a general-purpose i/o port rst reset pin dedicated reset pin in mb95f562h/f563h/f564h 9 p62 e general-purpose i/o port high-current pin to10 8/16-bit composite timer ch. 1 output pin 10 p63 e general-purpose i/o port high-current pin to11 8/16-bit composite timer ch. 1 output pin 11 p64 e general-purpose i/o port high-current pin ec1 8/16-bit composite timer ch. 1 clock input pin 12 p00 d general-purpose i/o port high-current pin an00 a/d converter analog input pin 13 p01 d general-purpose i/o port high-current pin an01 a/d converter analog input pin 14 p02 d general-purpose i/o port high-current pin int02 external interrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 15 p03 d general-purpose i/o port high-current pin int03 external interrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin
mb95560h/570h/580h series ds702-00003-1v0-e 15 (continued) * : for the i/o circuit types, see ? i/o circuit type?. pin no. pin name i/o circuit type* function 16 p04 d general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin 17 p05 d general-purpose i/o port high-current pin int05 external interrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 18 p06 e general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 output pin 19 p07 e general-purpose i/o port high-current pin int07 external interrupt input pin 20 p12 f general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin
mb95560h/570h/580h series 16 ds702-00003-1v0-e s pin functions (mb 95570h series, 8 pins) * : for the i/o circuit types, see ? i/o circuit type?. pin no. pin name i/o circuit type* function 1v ss ? power supply pin (gnd) 2v cc ? power supply pin 3 c ? capacitor connection pin 4 pf2 a general-purpose i/o port rst reset pin dedicated reset pin in mb95f572h/f573h/f574h 5 p04 d general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin ec0 8/16-bit composite timer ch. 0 clock input pin 6 p05 d general-purpose i/o port high-current pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 7 p06 e general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 output pin 8 p12 f general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin
mb95560h/570h/580h series ds702-00003-1v0-e 17 pin functions (mb 95580h series, 32 pins) (continued) pin no. pin name i/o circuit type* function 1 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 2 pf0 b general-purpose i/o port x0 main clock input oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7c ? capacitor connection pin 8 pf2 a general-purpose i/o port rst reset pin dedicated reset pin in mb95f582h/f583h/f584h 9nc ? it is an internally connected pin. always leave it unconnected. 10 nc ? it is an internally connected pin. always leave it unconnected. 11 nc ? it is an internally connected pin. always leave it unconnected. 12 nc ? it is an internally connected pin. always leave it unconnected. 13 nc ? it is an internally connected pin. always leave it unconnected. 14 nc ? it is an internally connected pin. always leave it unconnected. 15 nc ? it is an internally connected pin. always leave it unconnected. 16 nc ? it is an internally connected pin. always leave it unconnected. 17 p01 d general-purpose i/o port high-current pin an01 a/d converter analog input pin 18 p02 d general-purpose i/o port high-current pin int02 external interrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 19 p03 d general-purpose i/o port high-current pin int03 external interrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin
mb95560h/570h/580h series 18 ds702-00003-1v0-e (continued) * : for the i/o circuit types, see ? i/o circuit type?. pin no. pin name i/o circuit type* function 20 p04 d general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin 21 p05 d general-purpose i/o port high-current pin int05 external interrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 22 p06 e general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 output pin 23 p12 f general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin 24 p07 e general-purpose i/o port high-current pin int07 external interrupt input pin 25 nc ? it is an internally connected pin. always leave it unconnected. 26 nc ? it is an internally connected pin. always leave it unconnected. 27 nc ? it is an internally connected pin. always leave it unconnected. 28 nc ? it is an internally connected pin. always leave it unconnected. 29 nc ? it is an internally connected pin. always leave it unconnected. 30 nc ? it is an internally connected pin. always leave it unconnected. 31 nc ? it is an internally connected pin. always leave it unconnected. 32 nc ? it is an internally connected pin. always leave it unconnected.
mb95560h/570h/580h series ds702-00003-1v0-e 19 pin functions (mb 95580h series, 16 pins) (continued) pin no. pin name i/o circuit type* function 1 pf0 b general-purpose i/o port x0 main clock input oscillation pin 2 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7 pf2 a general-purpose i/o port rst reset pin dedicated reset pin in mb95f582h/f583h/f584h 8 c ? capacitor connection pin 9 p02 d general-purpose i/o port high-current pin int02 external interrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 10 p01 d general-purpose i/o port high-current pin an01 a/d converter analog input pin 11 p03 d general-purpose i/o port high-current pin int03 external interrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin 12 p04 d general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin
mb95560h/570h/580h series 20 ds702-00003-1v0-e (continued) * : for the i/o circuit types, see ? i/o circuit type?. pin no. pin name i/o circuit type* function 13 p05 d general-purpose i/o port high-current pin int05 external interrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 clock input pin 14 p06 e general-purpose i/o port high-current pin int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 clock input pin 15 p07 e general-purpose i/o port high-current pin int07 external interrupt input pin 16 p12 f general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin
mb95560h/570h/580h series ds702-00003-1v0-e 21 i/o circuit type (continued) type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance: approx.10 m ? cmos output ? hysteresis input ? pull-up control available n-ch re s et output / di g ital output re s et input / hy s tere s i s input s tandby control / port s elect clock input port s elect di g ital output di g ital output s tandby control hy s tere s i s input di g ital output di g ital output s tandby control hy s tere s i s input port s elect x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a s tandby control / port s elect n-ch p-ch port s elect di g ital output di g ital output s tandby control hy s tere s i s input n-ch di g ital output di g ital output di g ital output s tandby control hy s tere s i s input p-ch r pull-up control port s elect p-ch r pull-up control
mb95560h/570h/580h series 22 ds702-00003-1v0-e (continued) type circuit remarks d ? cmos output ? hysteresis input ? pull-up control available ? analog input e ? cmos output ? hysteresis input ? pull-up control available f ? n-ch open drain output ? hysteresis input n-ch p-ch p-ch r pull-up control di g ital output di g ital output analo g input a/d control s tandby control hy s tere s i s input n-ch p-ch p-ch r pull-up control di g ital output di g ital output s tandby control hy s tere s i s input n-ch s tandby control hy s tere s i s input di g ital output
mb95560h/570h/580h series ds702-00003-1v0-e 23 notes on device handling ? preventing latch-ups when using the device, ensure that the voltage applied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in "1. absolute maximum ratings" of " electrical characteristics" is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. ? stabilizing supply voltage supply voltage must be stabilized. a malfunction may occur when power supply voltage fluc tuates rapidly even though the fluctuation is within the guaranteed operating range of the v cc power supply voltage. as a rule of voltage stabilizatio n, suppress voltage fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuation rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. ? notes on using the external clock when an external clock is used, oscillation stabilizatio n wait time is required fo r power-on reset, wake-up from subclock mode or stop mode. pin connection ? treatment of unused pins if an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. always pull up or pull down an unused input pin through a resistor of at least 2 k . set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. if there is an unused output pin, leave it unconnected. ? power supply pins to reduce unnecessary electro-magnetic emission, prev ent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addition, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a ceramic capacitor of approximately 0.1 f as a bypass capacitor between the v cc pin and the v ss pin at a location close to this device. ? dbg pin connect the dbg pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the dbg pin and the v cc or v ss pin when designing the layout of the printed circuit board. the dbg pin should not stay at ?l? level after power-on until the reset output is released. ? rst pin connect the rst pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the rst pin and the v cc or v ss pin when designing the layout of the printed circuit board. the rst /pf2 pin functions as the reset input/output pin after power-on. in addition, the reset output of the rst /pf2 pin can be enabled by the rstoe bit in the sysc register, and the reset input function and the general purpose i/o function can be selected by the rste n bit in the sysc register.
mb95560h/570h/580h series 24 ds702-00003-1v0-e ? c pin use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. c c s dbg r s t ? dbg/rst /c pins connection diagram
mb95560h/570h/580h series ds702-00003-1v0-e 25 block diagram (mb95560h series) re s et with lvd d ua l oper a tion fl as h with s ec u rity f u nction ( 8 /12/20 k b yte) new- 8 fx cpu ram (240/496 b yte s ) interr u pt controller o s cill a tor circ u it cr o s cill a tor clock control on-chip de bu g wild regi s ter extern a l interr u pt lin-uart 8 /16- b it compo s ite timer ch. 0 8 /10- b it a/d converter 8 /16- b it compo s ite timer ch. 1 port port pf2 *1 /r s t *2 pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 p02 * 3 /int02 to p07 * 3 /int07 (p02 * 3 / s ck) (p0 3 * 3 / s ot) (p04/ s in) c (p12 *1 /dbg) (p05 * 3 /to00) (p06 * 3 /to01) p12 *1 /ec0, (p04/ec0) (p00 * 3 /an00 to p05 * 3 /an05) (p62 * 3 /to10) (p6 3 * 3 /to11) p64 * 3 /ec1 vcc v ss *1: *2: * 3 : pf2 a nd p12 a re n-ch open dr a in pin s . s oftw a re option p00 to p0 3 , p05 to p07 a nd p62 to p64 a re high-c u rrent pin s . intern a l bus note: pin s in p a renthe s e s indic a te th a t f u nction s of tho s e pin s a re s h a red a mong different re s o u rce s .
mb95560h/570h/580h series 26 ds702-00003-1v0-e block diagram (mb95570h series) re s et with lvd d ua l oper a tion fl as h with s ec u rity f u nction ( 8 /12/20 k b yte) new- 8 fx cpu ram (240/496 b yte s ) interr u pt controller cr o s cill a tor clock control on-chip de bu g wild regi s ter extern a l interr u pt 8 /16- b it compo s ite timer ch. 0 8 /10- b it a/d converter port port pf2 *1 /r s t *2 p04/int04, p06 * 3 /int06 c (p12 *1 /dbg) (p05 * 3 /to00) (p06 * 3 /to01) p12 *1 /ec0, (p04/ec0) p05 * 3 /an05, (p04/an04) vcc v ss *1: *2: * 3 : pf2 a nd p12 a re n-ch open dr a in pin s . s oftw a re option p05 a nd p06 a re high-c u rrent pin s . intern a l bus note: pin s in p a renthe s e s indic a te th a t f u nction s of tho s e pin s a re s h a red a mong different re s o u rce s .
mb95560h/570h/580h series ds702-00003-1v0-e 27 block diagram (mb95580h series) re s et with lvd d ua l oper a tion fl as h with s ec u rity f u nction ( 8 /12/20 k b yte) new- 8 fx cpu ram (240/496 b yte s ) interr u pt controller o s cill a tor circ u it cr o s cill a tor clock control on-chip de bu g wild regi s ter extern a l interr u pt lin-uart 8 /16- b it compo s ite timer ch. 0 8 /10- b it a/d converter port port pf2 *1 /r s t *2 pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 p02 * 3 /int02 to p07 * 3 /int07 (p02 * 3 / s ck) (p0 3 * 3 / s ot) (p04/ s in) c (p12 *1 /dbg) (p05 * 3 /to00) (p06 * 3 /to01) p12 *1 /ec0, (p04/ec0) (p01 * 3 /an01 to p05 * 3 /an05) vcc v ss *1: *2: * 3 : pf2 a nd p12 a re n-ch open dr a in pin s . s oftw a re option p01 to p0 3 a nd p05 to p07 a re high-c u rrent pin s . intern a l bus note: pin s in p a renthe s e s indic a te th a t f u nction s of tho s e pin s a re s h a red a mong different re s o u rce s .
mb95560h/570h/580h series 28 ds702-00003-1v0-e cpu core ? memory space the memory space of the mb95560h/570h/580h series is 64 kbyte in size, and consists of an i/o area, a data area, and a program area. the memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. the memory maps of the mb95560h/570h/580h series are shown below. ? memory maps i/o acce ss prohi b ited ram 496 b yte s regi s ter acce ss prohi b ited exten s ion i/o acce ss prohi b ited fl as h 20 k b yte 0000 h 00 8 0 h 0090 h 0100 h 0200 h 02 8 0 h 0f 8 0 h 1000 h b000 h ffff h mb95f564h/f564k/f574h / f574k/f5 8 4h/f5 8 4k i/o acce ss prohi b ited ram 496 b yte s regi s ter acce ss prohi b ited acce ss prohi b ited exten s ion i/o acce ss prohi b ited fl as h 8 k b yte 0000 h 00 8 0 h 0090 h 0100 h 02 8 0 h 0200 h 0f 8 0 h 1000 h b000 h c000 h e000 h ffff h mb95f56 3 h/f56 3 k/f57 3 h/ f57 3 k/f5 83 h/f5 83 k i/o acce ss prohi b ited ram 240 b yte s regi s ter acce ss prohi b ited exten s ion i/o acce ss prohi b ited acce ss prohi b ited fl as h 4 k b yte fl as h 4 k b yte fl as h 4 k b yte 0000 h 00 8 0 h 0090 h 0100 h 01 8 0 h 0f 8 0 h 1000 h b000 h c000 h f000 h ffff h mb95f562h/f562k/f572h/ f572k/f5 8 2h/f5 8 2k
mb95560h/570h/580h series ds702-00003-1v0-e 29 i/o map (mb95560h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w xxx11011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r/w xxxxxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00xx0000 b 000d h sycc2 system clock control register 2 r/w xxxx0011 b 000e h stbc2 standby control register 2 r/w 00000000 b 000f h to 0015 h ? (disabled) ? ? 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0032 h ? (disabled) ? ? 0033 h pul6 port 6 pull-up register r/w 00000000 b 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 r/w 00000000 b 0038 h t11cr1 8/16-bit composite timer 11 status control register 1 r/w 00000000 b 0039 h t10cr1 8/16-bit composite timer 10 status control register 1 r/w 00000000 b 003a h to 0048 h ? (disabled) ? ?
mb95560h/570h/580h series 30 ds702-00003-1v0-e (continued) address register abbreviation register name r/w initial value 0049 h eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 00000000 b 004c h , 004d h ? (disabled) ? ? 004e h lvdr lvdr reset voltage select ion id register r/w 00000000 b 004f h ? (disabled) ? ? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart receive/transmit data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communication control register r/w 000000xx b 0056 h to 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register upper r/w 00000000 b 006f h addl 8/10-bit a/d converter data register lower r/w 00000000 b 0070 h ? (disabled) ? ? 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector write control register 0 r/w 00000000 b 0074 h fsr3 flash memory stat us register 3 r 000xxxxx b 0075 h fsr4 flash memory status register 4 r/w 00000000 b 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch. 0 r/w 00000000 b
mb95560h/570h/580h series ds702-00003-1v0-e 31 (continued) address register abbreviation register name r/w initial value 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 00000000 b 0f97 h t11cr0 8/16-bit composite timer 11 status control register 0 r/w 00000000 b 0f98 h t10cr0 8/16-bit composite timer 10 status control register 0 r/w 00000000 b 0f99 h t11dr 8/16-bit composite timer 11 data register r/w 00000000 b 0f9a h t10dr 8/16-bit composite timer 10 data register r/w 00000000 b 0f9b h tmcr1 8/16-bit composite timer 10/11 timer mode control register r/w 00000000 b 0f9c h to 0fbb h ? (disabled) ? ? 0fbc h bgr1 lin-uart baud rate generator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h to 0fc2 h ? (disabled) ? ? 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 000xxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 000xxxxx b 0fe6 h ? (disabled) ? ? 0fe7 h crtda main cr clock temperature dependent adjustment register r/w 00011111 b 0fe8 h sysc system configuration register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r/w 00000000 b
mb95560h/570h/580h series 32 ds702-00003-1v0-e (continued) ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0feb h wdth watchdog timer selection id register (upper) r/w xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r/w xxxxxxxx b 0fed h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95560h/570h/580h series ds702-00003-1v0-e 33 i/o map (mb95570h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w xxx11011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r/w xxxxxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00xx0000 b 000d h sycc2 system clock control register 2 r/w xxxx0011 b 000e h stbc2 standby control register 2 r/w 00000000 b 000f h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h , 002b h ? (disabled) ? ? 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0032 h ? (disabled) ? ? 0033 h pul6 port 6 pull-up register r/w 00000000 b 0034 h , 0035 h ? (disabled) ? ? 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 r/w 00000000 b 0038 h to 0049 h ? (disabled) ? ? 004a h eic20 external interrupt circuit control register ch. 4 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6 r/w 00000000 b 004c h , 004d h ? (disabled) ? ? 004e h lvdr lvdr reset voltage select ion id register r/w 00000000 b 004f h to 006b h ? (disabled) ? ?
mb95560h/570h/580h series 34 ds702-00003-1v0-e (continued) address register abbreviation register name r/w initial value 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register upper r/w 00000000 b 006f h addl 8/10-bit a/d converter data register lower r/w 00000000 b 0070 h ? (disabled) ? ? 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector write control register 0 r/w 00000000 b 0074 h fsr3 flash memory stat us register 3 r 000xxxxx b 0075 h fsr4 flash memory status register 4 r/w 00000000 b 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h , 007c h ? (disabled) ? ? 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch. 0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 00000000 b 0f97 h to 0fc2 h ? (disabled) ? ?
mb95560h/570h/580h series ds702-00003-1v0-e 35 (continued) ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 000xxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 000xxxxx b 0fe6 h ? (disabled) ? ? 0fe7 h crtda main cr clock temperature dependent adjustment register r/w 00011111 b 0fe8 h sysc system configuration register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r/w 00000000 b 0feb h wdth watchdog timer selection id register (upper) r/w xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r/w xxxxxxxx b 0fed h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95560h/570h/580h series 36 ds702-00003-1v0-e i/o map (mb95580h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w xxx11011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r/w xxxxxxxx b 000a h tbtc time-base timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00xx0000 b 000d h sycc2 system clock control register 2 r/w xxxx0011 b 000e h stbc2 standby control register 2 r/w 00000000 b 000f h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0032 h ? (disabled) ? ? 0033 h pul6 port 6 pull-up register r/w 00000000 b 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 status control register 1 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 status control register 1 r/w 00000000 b 0038 h to 0048 h ? (disabled) ? ? 0049 h eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 00000000 b 004c h , 004d h ? (disabled) ? ? 004e h lvdr lvdr reset voltage select ion id register r/w 00000000 b 004f h ? (disabled) ? ?
mb95560h/570h/580h series ds702-00003-1v0-e 37 (continued) address register abbreviation register name r/w initial value 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart receive/transmit data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communication control register r/w 000000xx b 0056 h to 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register upper r/w 00000000 b 006f h addl 8/10-bit a/d converter data register lower r/w 00000000 b 0070 h ? (disabled) ? ? 0071 h fsr2 flash memory status register 2 r/w 00000000 b 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector write control register 0 r/w 00000000 b 0074 h fsr3 flash memory stat us register 3 r 000xxxxx b 0075 h fsr4 flash memory status register 4 r/w 00000000 b 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ? ? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ? (disabled) ? ? 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setting register (upper) ch. 0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch. 0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch. 2 r/w 00000000 b
mb95560h/570h/580h series 38 ds702-00003-1v0-e (continued) ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 status control register 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 status control register 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 00000000 b 0f97 h to 0fbb h ? (disabled) ? ? 0fbc h bgr1 lin-uart baud rate generator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h to 0fc2 h ? (disabled) ? ? 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 000xxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 000xxxxx b 0fe6 h ? (disabled) ? ? 0fe7 h crtda main cr clock temperature dependent adjustment r/w 00011111 b 0fe8 h sysc system configuration register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r/w 00000000 b 0feb h wdth watchdog timer selection id register (upper) r/w xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r/w xxxxxxxx b 0fed h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95560h/570h/580h series ds702-00003-1v0-e 39 interrupt source tabl e (mb95560h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq00 fffa h fffb h l00 [1:0] high low external interrupt ch. 5 irq01 fff8 h fff9 h l01 [1:0] external interrupt ch. 2 irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 fff4 h fff5 h l03 [1:0] external interrupt ch. 7 ? irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] lin-uart (reception) irq07 ffec h ffed h l07 [1:0] lin-uart (transmission) irq08 ffea h ffeb h l08 [1:0] ? irq09 ffe8 h ffe9 h l09 [1:0] ? irq10 ffe6 h ffe7 h l10 [1:0] ? irq11 ffe4 h ffe5 h l11 [1:0] ? irq12 ffe2 h ffe3 h l12 [1:0] ? irq13 ffe0 h ffe1 h l13 [1:0] 8/16-bit composite timer ch. 1 (upper) irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ? irq21 ffd0 h ffd1 h l21 [1:0] 8/16-bit composite timer ch. 1 (lower) irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0]
mb95560h/570h/580h series 40 ds702-00003-1v0-e interrupt source tabl e (mb95570h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq00 fffa h fffb h l00 [1:0] high low ? irq01 fff8 h fff9 h l01 [1:0] ? irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 ? irq03 fff4 h fff5 h l03 [1:0] ? ? irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] ? irq07 ffec h ffed h l07 [1:0] ? irq08 ffea h ffeb h l08 [1:0] ? irq09 ffe8 h ffe9 h l09 [1:0] ? irq10 ffe6 h ffe7 h l10 [1:0] ? irq11 ffe4 h ffe5 h l11 [1:0] ? irq12 ffe2 h ffe3 h l12 [1:0] ? irq13 ffe0 h ffe1 h l13 [1:0] ? irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ? irq21 ffd0 h ffd1 h l21 [1:0] ? irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0]
mb95560h/570h/580h series ds702-00003-1v0-e 41 interrupt source tabl e (mb95580h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq00 fffa h fffb h l00 [1:0] high low external interrupt ch. 5 irq01 fff8 h fff9 h l01 [1:0] external interrupt ch. 2 irq02 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 fff4 h fff5 h l03 [1:0] external interrupt ch. 7 ? irq04 fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 ffee h ffef h l06 [1:0] lin-uart (reception) irq07 ffec h ffed h l07 [1:0] lin-uart (transmission) irq08 ffea h ffeb h l08 [1:0] ? irq09 ffe8 h ffe9 h l09 [1:0] ? irq10 ffe6 h ffe7 h l10 [1:0] ? irq11 ffe4 h ffe5 h l11 [1:0] ? irq12 ffe2 h ffe3 h l12 [1:0] ? irq13 ffe0 h ffe1 h l13 [1:0] ? irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ? irq17 ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] time-base timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ? irq21 ffd0 h ffd1 h l21 [1:0] ? irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0]
mb95560h/570h/580h series 42 ds702-00003-1v0-e electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage * 1 v cc v ss ? 0.3 v ss + 6v input voltage * 1 v i v ss ? 0.3 v ss + 6v * 2 output voltage * 1 v o v ss ? 0.3 v ss + 6v * 2 maximum clamp current i clamp ? 2 + 2 ma applicable to specific pins * 3 total maximum clamp current |i clamp | ? 20 ma applicable to specific pins * 3 ?l? level maximum output current i ol1 ? 15 ma other than p05, p06, p62 and p63 * 4 i ol2 15 p05, p06, p62 and p63 * 4 ?l? level average current i olav1 ? 4 ma other than p05, p06, p62 and p63 * 4 average output current= operating current operating ratio (1 pin) i olav2 12 p05, p06, p62 and p63 * 4 average output current= operating current operating ratio (1 pin) ?l? level total maximum output current i ol ?48ma ?l? level total average output current i olav ?50ma total average output current= operating current operating ratio (total number of pins) ?h? level maximum output current i oh1 ? ? 15 ma other than p05, p06, p62 and p63 * 4 i oh2 ? 15 p05, p06, p62 and p63 * 4 ?h? level average current i ohav1 ? ? 4 ma other than p05, p06, p62 and p63 * 4 average output current= operating current operating ratio (1 pin) i ohav2 ? 8 p05, p06, p62 and p63 * 4 average output current= operating current operating ratio (1 pin) ?h? level total maximum output current i oh ?48ma ?h? level total average output current i ohav ? ? 50 ma total average output current= operating current operating ratio (total number of pins) power consumption pd ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb95560h/570h/580h series ds702-00003-1v0-e 43 (continued) * 1: the parameter is based on v ss = 0.0 v. * 2: v i and v o must not exceed v cc + 0.3 v. v i must not exceed the rated voltage. however, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. * 3: applicable to the following pins: p00 to p07, p62 to p64, pf0, pf1, pg1, pg2 (p00, and p62 to p64 are only available on mb95f562h/f562k/f563h/f563k/f564h/f564k. p01, p02, p03, p07, pf0. pf1, pg1 and pg2 are only available on mb95f562h/f562k/f563h/f563k/f564h/f564k/f582h/f582k/f583h/ f583k/f584h/f584k.) ? use under recommended operating conditions. ? use with dc volt age (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) signal and the microcontroller before applying the hv (high voltage) signal. ? the value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the hv (high voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. ? when the microcontroller drive current is low, such as in low power consumption modes, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microcontroller power supply is off (not fixed at 0 v), since power is supplied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit: * 4: p62 and p63 are only available on mb95f562h/f562k/f563h/f563k/f564h/f564k. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. hv(high volt a ge) inp u t (0 v to 16 v) protective diode v cc n-ch p-ch r limiting re s i s tor ? input/output equivalent circuit
mb95560h/570h/580h series 44 ds702-00003-1v0-e 2. recommended operating conditions (v ss = 0.0 v) * 1: the value varies depending on the operating frequency, the machine clock and the analog guaranteed range. * 2: the value is 2.88 v when the low-voltage detection reset is used. * 3: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within thei r recommended operating condition ranges. operation outside these ra nges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 2.4 * 1 * 2 5.5 * 1 v in normal operation other than on-chip debug mode 2.3 5.5 hold condition in stop mode 2.9 5.5 in normal operation on-chip debug mode 2.3 5.5 hold condition in stop mode smoothing capacitor c s 0.022 1 f * 3 operating temperature t a ? 40 + 85 c other than on-chip debug mode + 5 + 35 on-chip debug mode c c s dbg * s ince the dbg pin b ecome s a comm u nic a tion pin in on-chip de bu g mode, s et a p u ll- u p re s i s tor v a l u e su iting the inp u t/o u tp u t s pecific a tion s of p12/ec0/dbg. *: r s t ?dbg / rst / c pins connection diagram
mb95560h/570h/580h series ds702-00003-1v0-e 45 3. dc characteristics (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ *1 max *2 "h" level input voltage v ih p04 ? 0.7 v cc ?v cc + 0.3 v hysteresis input v ihs p00 * 3 to p03 * 4 , p05 to p07 * 4 , p12, p62 to p64 * 3 , pf0 * 4 , pf1 * 4 , pg1 * 4 , pg2 * 4 ?0.8 v cc ?v cc + 0.3 v hysteresis input v ihm pf2 ? 0.8 v cc ?v cc + 0.3 v hysteresis input ?l? level input voltage v il p04 ? v ss ? 0.3 ? 0.3 v cc v hysteresis input v ils p00 * 3 to p03 * 4 , p05 to p07 * 4 , p12, p62 to p64 * 3 , pf0 * 4 , pf1 * 4 , pg1 * 4 , pg2 * 4 ?v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss ? 0.3 ? 0.2 v cc v hysteresis input open-drain output application voltage v d p12, pf2 ? v ss ? 0.3 ? vss + 5.5 v ?h? level output voltage v oh1 p04, pf0 * 4 , pf1 * 4 , pg1 * 4 , pg2 * 4 i oh = ? 4 ma v cc ? 0.5 ? ? v v oh2 p00 * 3 to p03 * 4 , p05 to p07 * 4 , p62 to p64 * 3 i oh = ? 8 ma v cc ? 0.5 ? ? v ?l? level output voltage v ol1 p04, p12 pf0 to pf2 * 4 , pg1 * 4 , pg2 * 4 i ol = 4 ma ? ? 0.4 v v ol2 p00 * 3 to p03 * 4 , p05 to p07 * 4 , p12, p62 to p64 * 3 i ol = 12 ma ? ? 0.4 v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc ? 5? + 5a when pull-up resistance is disabled pull-up resistance r pull p00 * 3 to p07 * 4 , p62 to p64 * 3 , pg1 * 4 , pg2 * 4 * 5 v i = 0 v 25 50 100 k when pull-up resistance is enabled input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf
mb95560h/570h/580h series 46 ds702-00003-1v0-e (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ *1 max *2 power supply current * 5 i cc v cc (external clock operation) f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?3.65.8ma except during flash memory writing and erasing ?7.513.8ma during flash memory writing and erasing ? 4.1 9.1 ma at a/d conversion i ccs f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?1.3 3ma i ccl f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = + 25 c ?49145a i ccls * 6 f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = + 25 c ?610a i cct * 6 f cl = 32 khz watch mode main stop mode t a = + 25 c ?5 9a i ccmcr v cc f crh = 4 mhz f mp = 4 mhz main cr clock mode ?1.14.6ma i ccscr sub-cr clock mode (divided by 2) t a = + 25 c ? 58.1 230 a i ccts v cc (external clock operation) f ch = 32 mhz time-base timer mode t a = + 25 c ?330370a i cch substop mode t a = + 25 c ?415a main stop mode for a single external clock product
mb95560h/570h/580h series ds702-00003-1v0-e 47 (continued) (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = ? 40 c to + 85 c) * 1: v cc = 5.0 v, t a = + 25 c * 2: v cc = 5.5 v, t a = + 25 c * 3: p00, p62, p63 and p64 are available only on mb95f562h/f562k/f563h/f563k/f564h/f564k. * 4: p01, p02, p03, p07, pf0, pf1, pg1 and pg2 are available only on mb95f562h/f562k/f563h/f563k/ f564h/f564k/f582h/f582k/f583h/f583k/f584h/f584k. * 5: ? the power supply current is determined by the external clock. when the low-voltage detection option is selected, the power-supply current will be the sum of adding the current consumption of the low-voltage detection circuit (i lv d ) to one of the value from i cc to i cch . in addition, when both the low-voltage detection option and the cr oscillator are sele cted, the power supply current will be the sum of adding up the current consumption of the low-voltage det ection circuit, the current cons umption of the cr oscillators (i crh , i crl ) and a specified value. in on-chi p debug mode, the cr oscillator (i crh ) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. ? see "4. ac characteristics: (1) clock timing" for f ch and f cl . ? see "4. ac characteristics: (2) source clock / machine clock" for f mp and f mpl . * 6: in sub-cr clock mode, the power supply cu rrent value will become the sum of adding i crl to i ccls or i cct . in addition, when the sub-cr clock mode is selected with f mpl being 50 khz, the current consumption will increase accordingly. parameter symbol pin name condition value unit remarks min typ *1 max *2 power supply current * 5 i lvd v cc current consumption for low-voltage detection circuit only ?4 7a i crh current consumption for the main cr oscillator ?240320a i crl current consumption for the sub-cr oscillator oscillating at 100 khz ?720a
mb95560h/570h/580h series 48 ds702-00003-1v0-e 4. ac characteristics (1) clock timing (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0 x1 : open 1 ? 12 mhz when the main external clock is used x0, x1 * 1?32.5mhz f crh ? ? 3.92 4 4.08 mhz operating conditions ? the main cr clock is used. ?0 c < t a < + 70 c 3.8 4 4.2 mhz operating conditions ? the main cr clock is used. ? ? 40 c t a < 0 c, + 70 c < t a + 85 c 7.84 8 8.16 mhz operating conditions ? pll multiplier: 2 ?0 c < t a < + 70 c 7.6 8 8.4 mhz operating conditions ? pll multiplier: 2 ? ? 40 c t a < 0 c, + 70 c < t a + 85 c 9.8 10 10.2 mhz operating conditions ? pll multiplier: 2.5 ?0 c < t a < + 70 c 9.5 10 10.5 mhz operating conditions ? pll multiplier: 2.5 ? ? 40 c t a < 0 c, + 70 c < t a + 85 c 11.76 12 12.24 mhz operating conditions ? pll multiplier: 3 ?0 c < t a < + 70 c 11.4 12 12.6 mhz operating conditions ? pll multiplier: 3 ? ? 40 c t a < 0 c, + 70 c < t a + 85 c 15.68 16 16.32 mhz operating conditions ? pll multiplier: 4 ?0 c < t a < + 70 c 15.2 16 16.8 mhz operating conditions ? pll multiplier: 4 ? ? 40 c t a < 0 c, + 70 c < t a + 85 c f cl x0a, x1a ? ? 32.768 ? khz when the sub-oscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ?50100150khz when the sub-cr clock is used
mb95560h/570h/580h series ds702-00003-1v0-e 49 (continued) (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : the external clock signal is input to x0 and the inverted external clock signal to x1. parameter symbol pin name condition value unit remarks min typ max clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0 x1 : open 83.4 ? 1000 ns when an external clock is used x0, x1 * 30.8 ? 1000 ns t lcyl x0a, x1a ? ? 30.5 ? s when the subclock is used input clock pulse width t wh1 t wl1 x0 x1 : open 33.4 ? ? ns when an external clock is used, the duty ratio should range between 40% and 60%. x0, x1 * 14.4 ? ? ns t wh2 t wl2 x0a ? ? 15.2 ? s input clock rise time and fall time t cr t cf x0 x1 : open ? ? 5 ns when an external clock is used x0, x1 * ?? 5ns cr oscillation start time t crhwk ? ? ? ? 50 s when the main cr clock is used t crlwk ? ? ? ? 30 s when the sub-cr clock is used
mb95560h/570h/580h series 50 ds702-00003-1v0-e x0, x1 0. 8 v cc 0.2 v cc 0.2 v cc 0. 8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf ? input waveform generated when an external clock (main clock) is used when a cry s t a l o s cill a tor or a cer a mic o s cill a tor i s us ed when a n extern a l clock i s us ed x0 x1 x0 x1 f ch f ch when a n extern a l clock i s us ed (x1 i s open) x0 x1 open f ch ? figure of main clock input port external connection x0a 0. 8 v cc 0.2 v cc 0.2 v cc 0. 8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf ? input waveform generated when an external clock (subclock) is used when a cry s t a l o s cill a tor or a cer a mic o s cill a tor i s us ed when a n extern a l cloc k i s us ed x0a x1a x0a x1a open f cl f cl ? figure of subclock input port external connection
mb95560h/570h/580h series ds702-00003-1v0-e 51 (2) source clock / machine clock (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) * 1: this is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits (sycc:div1, di v0). this source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (sycc : div1, div0). in addition, a source clock can be selected from the following. ? main clock divided by 2 ? pll multiplication of main clock (select a multiplier from 2, 2.5, 3 and 4.) ? main cr clock ? subclock divided by 2 ? sub-cr clock divided by 2 * 2: this is the operating clock of the microcontroller. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter symbol pin name value unit remarks min typ max source clock cycle time * 1 t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 62.5 ? 1000 ns when the main cr clock is used min: f crh = 4 mhz, multiplied by 4 max: f crh = 4 mhz, divided by 4 ?61?s when the sub-oscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-cr clock is used f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used ? 4 ? mhz when the main cr clock is used f spl ? 16.384 ? khz when the sub-oscillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time * 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 250 ? 1000 ns when the main cr clock is used min: f sp = 4 mhz, no division max: f sp = 4 mhz, divided by 4 61 ? 976.5 s when the sub-oscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.25 ? 16 mhz when the main cr clock is used f mpl 1.024 ? 16.384 khz when the sub- oscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz
mb95560h/570h/580h series 52 ds702-00003-1v0-e f ch (m a in o s cill a tion clock) divided b y 2 divided b y 2 divided b y 2 f mpll (m a in cr pll) f crh (m a in cr clock) f cl ( sub -o s cill a tion clock) f crl ( sub -cr clock) s clk ( s o u rce clock) mclk (m a chine clock) m a chine clock divide r a tio s elect b it s ( s ycc:div1, div0) clock mode s elect b it s ( s ycc2: rc s 1, rc s 0) divi s ion circ u it 1 1/4 1/ 8 1/16 ? schematic diagram of the clock generation block oper a ting volt a ge (v) a/d converter oper a tion r a nge 5.5 5.0 4.0 3 .5 3 .0 2.7 2.4 16 khz 3 mhz 10 mhz 16.25 mhz s o u rce clock fre qu ency (f s p /f s pl ) oper a ting volt a ge (v) a/d converter oper a tion r a nge 5.5 5.0 4.0 3 .5 3 .0 2.9 16 khz 3 mhz 12.5 mhz 16.25 mhz s o u rce clock fre qu ency (f s p ) ? operating voltage - operating frequency (when t a = ? 40 c to + 85 c) mb95560h/570h/580h (without the on-chip debug function) ? operating voltage - operating frequency (when t a = ? 40 c to + 85 c) mb95560h/570h/580h (with the on-chip debug function)
mb95560h/570h/580h series ds702-00003-1v0-e 53 (3) external reset (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) * 1: see ?(2) source clock / machine clock? for t mclk . * 2: the oscillation time of an oscillator is the time for it to reach 90% of its amplitude. the crystal oscillator has an oscillation time of between seve ral ms and tens of ms. the ceramic oscillator has an oscillation time of between hundreds of s and several ms. the external clock has an oscillation time of 0 ms. the cr oscillator clock has an oscillation time of between several s and several ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns in normal operation oscillation time of the oscillator * 2 + 200 ?s in stop mode, subclock mode, subsleep mode, watch mode, and power-on 200 ? s in time-base timer mode 0.2 v cc r s t 0.2 v cc t r s tl t r s tl 0.2 v cc 0.2 v cc 200 s x0 intern a l oper a ting clock 90 % of a mplit u de o s cill a tion time of o s cill a tor o s cill a tion s t ab iliz a tion w a it time exec u te in s tr u ction intern a l re s et r s t ? in normal operation ? in stop mode, subclock mode, subsleep mode, watch mode and power-on
mb95560h/570h/580h series 54 ds702-00003-1v0-e (4) power-on reset (v ss = 0.0 v, t a = ? 40 c to + 85 c) note: a sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mv/ms as shown below. parameter symbol condition value unit remarks min max power supply rising time t r ??50ms power supply cutoff time t off ? 1 ? ms wait time until power-on 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2. 3 v v ss hold condition in s top mode s et the s lope of ri s ing to a v a l u e b elow 3 0 mv/m s .
mb95560h/570h/580h series ds702-00003-1v0-e 55 (5) peripheral input timing (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) * 1: see ?(2) source clock / machine clock? for t mclk . * 2: int04, int06 and ec0 are available on all products. * 3: int02, int03, int05 and int07 are available only on mb95f562h/f562k/f563h/f563k/f564h/f564k/ f582h/f582k/f583h/f583k/f584h/f584k. * 4: ec1 is available only on mb95f562h/f562k/f563h/f563k/f564h/f564k. parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int02 to int07 * 2, * 3 , ec0 * 2 , ec1 * 4 2 t mclk * 1 ?ns peripheral input ?l? pulse width t ihil 2 t mclk * 1 ?ns int02 to int07 *2, * 3 , ec0 *2 , ec1 *4 0. 8 v cc 0. 8 v cc 0.2 v cc 0.2 v cc t ilih t ihil
mb95560h/570h/580h series 56 ds702-00003-1v0-e (6) lin-uart timing (available only on mb95f562h/f562k/f563h/f563k/f564h/f564k/f582h/f582k/ f583h/f583k/f584h/f584k) sampling is executed at the rising edge of the sampling clock * 1 , and serial clock delay is disabled * 2 . (escr register: sces bit = 0 , eccr register: scde bit = 0) (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) * 1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. * 2: the serial clock delay function is a function used to de lay the output signal of the serial clock for half the clock. * 3: see ?(2) source clock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t slovi sck, sot ? 50 + 50 ns valid sin sck t ivshi sck, sin t mclk * 3 + 80 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin: c l = 80 pf + 1 ttl 3 t mclk * 3 ? t r ?ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 10 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 60 ns valid sin sck t ivshe sck, sin 30 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 30 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95560h/570h/580h series ds702-00003-1v0-e 57 0.2 v cc 0.2 v cc 0. 8 v cc t s lovi t iv s hi t s hixi 0. 8 v cc 0.2 v cc s ck s ot s in 0.7 v cc 0. 3 v cc 0.7 v cc 0. 3 v cc t s cyc ? internal shift clock mode 0.2 v cc 0.2 v cc 0. 8 v cc 0. 8 v cc t s love t iv s he t s hixe 0. 8 v cc 0.2 v cc s ck s ot s in 0.7 v cc 0. 3 v cc 0.7 v cc 0. 3 v cc t s l s h t s h s l t r 0. 8 v cc t f ? external shift clock mode
mb95560h/570h/580h series 58 ds702-00003-1v0-e sampling is executed at the falling edge of the sampling clock * 1 , and serial clock delay is disabled * 2 . (escr register: sces bit = 1 , eccr register: scde bit = 0) (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) * 1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. * 2: the serial clock delay function is a function used to de lay the output signal of the serial clock for half the clock. * 3: see ?(2) source clock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t shovi sck, sot ? 50 + 50 ns valid sin sck t ivsli sck, sin t mclk * 3 + 80 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin: c l = 80 pf + 1 ttl 3 t mclk * 3 ? t r ?ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 10 ? ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 60 ns valid sin sck t ivsle sck, sin 30 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 30 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95560h/570h/580h series ds702-00003-1v0-e 59 0.2 v cc 0. 8 v cc 0. 8 v cc t s hovi t iv s li t s lixi 0. 8 v cc 0.2 v cc s ck s ot s in 0.7 v cc 0. 3 v cc 0.7 v cc 0. 3 v cc t s cyc ? internal shift clock mode 0.2 v cc 0.2 v cc 0.2 v cc 0. 8 v cc t s hove t iv s le t s lixe 0. 8 v cc 0.2 v cc s ck s ot s in 0.7 v cc 0. 3 v cc 0.7 v cc 0. 3 v cc t s h s l t s l s h t f 0. 8 v cc t r ? external shift clock mode
mb95560h/570h/580h series 60 ds702-00003-1v0-e sampling is executed at the rising edge of the sampling clock* 1 , and serial clock delay is enabled * 2 . (escr register: sces bit = 0 , eccr register: scde bit = 1) (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) * 1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. * 2: the serial clock delay function is a function that de lays the output signal of the serial clock for half clock. * 3: see ?(2) source clock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t shovi sck, sot ? 50 + 50 ns valid sin sck t ivsli sck, sin t mclk * 3 + 80 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot 3 t mclk * 3 ? 70 ? ns 0. 8 v cc 0.2 v cc 0.2 v cc t s hovi t s ovli t iv s li t s lixi 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc s ck s ot s in 0.7 v cc 0. 3 v cc 0.7 v cc 0. 3 v cc t s cyc
mb95560h/570h/580h series ds702-00003-1v0-e 61 sampling is executed at the falling edge of the sampling clock * 1 , and serial clock delay is enabled * 2 . (escr register: sces bit = 1 , eccr register: scde bit = 1) (v cc = 5.0 v 10%, v ss = 0.0 v, t a = ? 40 c to + 85 c) * 1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. * 2: the serial clock delay function is a function that de lays the output signal of the serial clock for half clock. * 3: see ?(2) source clock / machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operating output pin: c l = 80 pf + 1 ttl 5 t mclk * 3 ?ns sck sot delay time t slovi sck, sot ? 50 + 50 ns valid sin sck t ivshi sck, sin t mclk * 3 + 80 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot 3 t mclk * 3 ? 70 ? ns 0.2 v cc 0. 8 v cc 0. 8 v cc t s lovi t s ovhi t iv s hi t s hixi 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc s ck s ot s in 0.7 v cc 0. 3 v cc 0.7 v cc 0. 3 v cc t s cyc
mb95560h/570h/580h series 62 ds702-00003-1v0-e (7) low-voltage detection (v ss = 0.0 v, t a = ? 40 c to + 85 c) * : the release voltage and the detection voltage can be selected by using the lvd reset voltage selection id register (lvdr) in the low-voltage detection reset circuit. for details of the lvdr register, refer to ?chapter 18 low-voltage detection reset circuit? in the hardware manual of the mb95560h/ 570h/580h series. parameter symbol value unit remarks min typ max release voltage * v dl + 2.52 2.7 2.88 v at power supply rise 2.61 2.8 2.99 2.89 3.1 3.31 3.08 3.3 3.52 detection voltage * v dl ? 2.43 2.6 2.77 v at power supply fall 2.52 2.7 2.88 2.80 3 3.20 2.99 3.2 3.41 hysteresis width v hys ??100mv power supply start voltage v off ??2.3v power supply end voltage v on 4.9 ? ? v power supply voltage change time (at power supply rise) t r 650 ? ? s slope of power supply that the reset release signal generates within the rating (v dl+ ) power supply voltage change time (at power supply fall) t f 650 ? ? s slope of power supply that the reset detection signal generates within the rating (v dl- ) reset release delay time t d1 ? ? 30 s reset detection delay time t d2 ? ? 30 s lvd threshold voltage transition stabilization time t stb 10 ? ? s
mb95560h/570h/580h series ds702-00003-1v0-e 63 v hy s t d2 t d1 t r t f v cc v on v off v dl+ v dl- time time intern a l re s et s ign a l
mb95560h/570h/580h series 64 ds702-00003-1v0-e 5. a/d converter (1) a/d converter electrical characteristics (v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max resolution ? ??10bit total error ? 3? + 3lsb linearity error ? 2.5 ? + 2.5 lsb differential linear error ? 1.9 ? + 1.9 lsb zero transition voltage v ot v ss ? 7.2 lsb v ss + 0.5 lsb v ss + 8.2 lsb v full-scale transition voltage v fst v cc ? 6.2 lsb v cc ? 1.5 lsb v cc + 9.2 lsb v compare time ? 3 ? 10 s 2.7 v v cc 5.5 v sampling time ? 0.517 ? s 2.7 v v cc 5.5 v, with external impedance < 3.3 k analog input current i ain ? 0.3 ? + 0.3 a analog input voltage v ain v ss ?v cc v
mb95560h/570h/580h series ds702-00003-1v0-e 65 (2) notes on using the a/d converter ? external impedance of analog input and its sampling time ? the a/d converter has a sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting a/d conversion precision. therefore, to satisfy the a/d conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. in addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 f to the analog input pin. ? a/d conversion error as |v cc ? v ss | decreases, the a/d conversion error increases proportionately. note: the v a l u e s a re reference v a l u e s . 4.5 v v cc 5.5 v 2.7 v v cc < 5.5 v 3 . 3 k (m a x) 15.7 k (m a x) 14. 8 9 pf (m a x) v cc r c 14. 8 9 pf (m a x) comp a r a tor an a log inp u t d u ring sa mpling: on r c ? analog input equivalent circuit [extern a l imped a nce = 0 k to 100 k ] extern a l imped a nce [k ] minim u m sa mpling time [ s ] minim u m sa mpling time with v cc > 2.7 v minim u m sa mpling time with v cc > 2.4 v 0246 8 10 12 100000 8 0000 60000 40000 20000 0 [extern a l imped a nce = 0 k to 20 k ] extern a l imped a nce [k ] minim u m sa mpling time [ s ] 0 0.5 1 1.5 2 2.5 20000 15000 10000 5000 0 ? relationship between external impedance and minimum sampling time
mb95560h/570h/580h series 66 ds702-00003-1v0-e (3) definitions of a/d converter terms ? resolution it indicates the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. ? linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device to the full-scale transition point (?11 1111 1111? ?11 1111 1110?) of the same device. ? differential linear error (unit: lsb) it indicates how much the input voltage required to change the output code by 1 lsb deviates from an ideal value. ? total error (unit: lsb) it indicates the difference between an actual value and a theoretical value. the error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise. (continued) v f s t ide a l i/o ch a r a cteri s tic s 001 h 002 h 00 3 h 004 h 3 fd h 3 fe h 3 ff h digit a l o u tp u t digit a l o u tp u t 2 l s b v ot 1 l s b 0.5 l s b tot a l error an a log inp u t an a log inp u t 001 h 002 h 00 3 h 004 h 3 fd h 3 fe h 3 ff h act ua l conver s ion ch a r a cteri s tic ide a l ch a r a cteri s tic act ua l conver s ion ch a r a cteri s tic n v nt : a/d converter digit a l o u tp u t v a l u e : volt a ge a t which the digit a l o u tp u t tr a n s it s from (n - 1) h to n h {1 l s b (n-1) + 0.5 l s b} v nt tot a l error of digit a l o u tp u t n v nt - {1 l s b (n - 1) + 0.5 l s b} 1 l s b [l s b] = v cc - v ss 1024 (v) 1 l s b = v ss v cc v ss v cc
mb95560h/570h/580h series ds702-00003-1v0-e 67 (continued) zero tr a n s ition error line a rity error f u ll- s c a le tr a n s ition error 001 h 002 h 00 3 h 004 h 3 fd h 3 fe h 3 ff h digit a l o u tp u t differenti a l line a r error of digit a l o u tp u t n v (n+1)t - v nt 1 l s b - 1 = line a rity error of digit a l o u tp u t n v nt - {1 l s b n + v ot } 1 l s b = digit a l o u tp u t an a log inp u t 001 h 002 h 3 fc h 3 fd h 00 3 h 3 fe h 3 ff h 004 h act ua l conver s ion ch a r a cteri s tic act ua l conver s ion ch a r a cteri s tic v ot (me asu rement v a l u e) act ua l conver s ion ch a r a cteri s tic act ua l conver s ion ch a r a cteri s tic v f s t (me asu rement v a l u e) v ss v cc v ss v cc v ss v cc v ss v cc an a log inp u t digit a l o u tp u t an a log inp u t ide a l ch a r a cteri s tic {1 l s b n + v ot } act ua l conver s ion ch a r a cteri s tic ide a l ch a r a cteri s tic act ua l conver s ion ch a r a cteri s tic v ot (me asu rement v a l u e) v f s t (me asu rement v a l u e) v nt differenti a l line a rity error (n-2) h (n-1) h n h (n+1) h digit a l o u tp u t an a log inp u t act ua l conver s ion ch a r a cteri s tic ide a l ch a r a cteri s tic v nt act ua l conver s ion ch a r a cteri s tic v (n+1)t n v nt : a/d converter digit a l o u tp u t v a l u e : volt a ge a t which the digit a l o u tp u t tr a n s it s from (n - 1) h to n h v ot (ide a l v a l u e) = v ss + 0.5 l s b [v] v f s t (ide a l v a l u e) = v cc - 2 l s b [v] ide a l ch a r a cteri s tic
mb95560h/570h/580h series 68 ds702-00003-1v0-e 6. flash memory program/erase characteristics * 1: v cc = 5.5 v, t a = + 25 c, 0 cycle * 2: this value is converted fr om the result of a technolo gy reliability assessment. (t he value is converted from the result of a high temperature accelerated test using the arrhenius equation with the average temperature being + 85 c). parameter value unit remarks min typ max sector erase time (2 kbyte sector) ?0.3 * 1 1.6 s the time of writing 00 h prior to erasure is excluded. sector erase time (16 kbyte sector) ?0.6 * 1 3.1 s the time of writing 00 h prior to erasure is excluded. byte writing time ? 17 272 s system-level overhead is excluded. program/erase cycle 100000 ? ? cycle power supply voltage at program/erase 2.4 ? 5.5 v flash memory data retention time 5 * 2 ? ? year average t a = + 85 c
mb95560h/570h/580h series ds702-00003-1v0-e 69 sample characteristics ? power supply current temperature characteristics (continued) 0 5 10 15 20 2 3 4567 i cc [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 5 10 15 20 ? 50 0 + 50 + 100 + 150 i cc [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz 0 4 2 6 8 10 2 3 4567 i cc s [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 4 2 6 8 10 ? 50 0 + 50 + 100 + 150 i cc s [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz 0 25 50 75 100 2 3 4567 i ccl [ a] v cc [v] 0 25 50 75 100 ? 50 0 + 50 + 100 + 150 i ccl [ a] t a [ c] i cc ? v cc t a = + 25 c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the external clock operating i cc ? t a v cc = 5.5 v, f mp = 10, 16 mhz (divided by 2) main clock mode with the external clock operating i ccs ? v cc t a = + 25 c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccs ? t a v cc = 5.5 v, f mp = 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccl ? v cc t a = + 25 c, f mpl = 16 khz (divided by 2) subclock mode with the external clock operating i ccl ? t a v cc = 5.5 v, f mpl = 16 khz (divided by 2) subclock mode with the external clock operating
mb95560h/570h/580h series 70 ds702-00003-1v0-e (continued) 0 4 12 8 20 16 ? 50 0 + 50 + 100 + 150 i cct [ a] t a [ c] i cct ? t a v cc = 5.5 v, f mpl = 16 khz (divided by 2) watch mode with the external clock operating 0 10 3 0 20 60 8 0 70 50 40 ? 50 0 + 50 + 100 + 150 i ccl s [ a] t a [ c] i ccls ? t a v cc = 5.5 v, f mpl = 16 khz (divided by 2) subsleep mode with the external clock operating 0 20 10 40 3 0 70 8 0 60 50 2 3 4567 i ccl s [ a] v cc [v] 0 4 12 8 20 16 2 3 4567 i cct [ a] v cc [v] 0.0 0.2 0.4 0.6 1.4 1.2 1.0 0. 8 2 3 4567 i ct s [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0.0 0.2 0.6 0.4 1.0 0. 8 1.4 1.2 ? 50 0 + 50 + 100 + 150 i ct s [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz i ccls ? v cc t a = + 25 c, f mpl = 16 khz (divided by 2) subsleep mode with the external clock operating i cct ? v cc t a = + 25 c, f mpl = 16 khz (divided by 2) watch mode with the external clock operating i cts ? v cc t a = + 25 c, f mp = 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating i cts ? t a v cc = 5.5 v, f mp = 10, 16 khz (divided by 2) time-base timer mode with the external clock operating
mb95560h/570h/580h series ds702-00003-1v0-e 71 (continued) 0 5 10 15 20 ? 50 0 + 50 + 100 + 150 i cch [ a] t a [ c] i cch ? t a v cc = 5.5 v, f mpl = (stop) substop mode with the external clock stopping 0 5 15 20 10 2 3 4567 i cch [ a] v cc [v] 0 5 10 15 20 2 3 4567 i ccmcr [ma] v cc [v] 0 5 10 15 20 ? 50 0 + 50 + 100 + 150 i ccmcr [ma] t a [ c] 0 150 200 100 50 2 3 4567 i cc s cr [ a] v cc [v] 0 150 200 100 50 ? 50 0 + 50 + 100 + 150 i cc s cr [ a] t a [ c] i cch ? v cc t a = + 25 c, f mpl = (stop) substop mode with the external clock stopping i ccmcr ? v cc t a = + 25 c, f mp = 4 mhz (no division) main clock mode with the main cr clock operating i ccmcr ? t a v cc = 5.5 v, f mp = 4 mhz (no division) main clock mode with the main cr clock operating i ccscr ? v cc t a = + 25 c, f mpl = 50 khz (divided by 2) subclock mode with the sub-cr clock operating i ccscr ? t a v cc = 5.5 v, f mpl = 50 khz (divided by 2) subclock mode with th e sub-cr clock operating
mb95560h/570h/580h series 72 ds702-00003-1v0-e ? input voltage characteristics 0 1 2 4 3 5 2 3 45 7 6 v ihi /v ili [v] v cc [v] v ihi v ili 0 1 2 4 3 5 2 3 45 7 6 v ih s /v il s [v] v cc [v] v ih s v il s v ihi ? v cc and v ili ? v cc t a = + 25 c v ihs ? v cc and v ils ? v cc t a = + 25 c 0 1 2 4 3 5 2 3 45 7 6 v ihm /v ilm [v] v cc [v] v ihm v ilm v ihm ? v cc and v ilm ? v cc t a = + 25 c
mb95560h/570h/580h series ds702-00003-1v0-e 73 ? output voltage characteristics 0 ? 2 ? 4 i oh [ma] ? 6 ? 8 ? 10 1.0 0. 8 0.6 v cc ? v oh2 [v] 0.4 0.2 0.0 v cc = 2.4 v v cc = 2.7 v v cc = 3 .5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc ? v oh2 ) ? i oh t a = + 25 c 024 i ol [ma] 6 8 10 1.0 0. 8 0.6 v ol1 [v] 0.4 0.2 0.0 v cc = 2.4 v v cc = 2.7 v v cc = 3 .5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v ol1 ? i ol t a = + 25 c 0 ? 2 ? 4 i oh [ma] ? 6 ? 8 ? 10 1.0 0. 8 0.6 v cc ? v oh1 [v] 0.4 0.2 0.0 v cc = 2.4 v v cc = 2.7 v v cc = 3 .5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc ? v oh1 ) ? i oh t a = + 25 c 024 i ol [ma] 6 8 10 0.6 v ol2 [v] 0.4 0.2 0.0 v cc = 2.4 v v cc = 2.7 v v cc = 3 .5 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v ol2 ? i ol t a = + 25 c
mb95560h/570h/580h series 74 ds702-00003-1v0-e ? pull-up characteristics 0 50 150 100 250 200 2 3 456 r pull [k ] v cc [v] r pull ? v cc t a = + 25 c
mb95560h/570h/580h series ds702-00003-1v0-e 75 mask options no. part number mb95f562h mb95f563h mb95f564h mb95f572h mb95f573h mb95f574h mb95f582h mb95f583h mb95f584h mb95f562k mb95f563k mb95f564k mb95f572k mb95f573k mb95f574k mb95f582k mb95f583k mb95f584k selectable/fixed fixed 1 low-voltage detection reset without low-voltage detection reset with low-voltage detection reset 2 reset with dedicated reset input without dedicated reset input
mb95560h/570h/580h series 76 ds702-00003-1v0-e ordering information part number package mb95f562hwqn-g-jne1 mb95f562hwqn-g-jnere1 mb95f562kwqn-g-jne1 mb95f562kwqn-g-jnere1 mb95f563hwqn-g-jne1 mb95f563hwqn-g-jnere1 mb95f563kwqn-g-jne1 mb95f563kwqn-g-jnere1 mb95f564hwqn-g-jne1 mb95f564hwqn-g-jnere1 mb95f564kwqn-g-jne1 mb95f564kwqn-g-jnere1 32-pin plastic qfn (lcc-32p-m19) mb95f562hpf-g-jne2 mb95f562kpf-g-jne2 mb95f563hpf-g-jne2 mb95f563kpf-g-jne2 mb95f564hpf-g-jne2 mb95f564kpf-g-jne2 20-pin plastic sop (fpt-20p-m09) mb95f562hpft-g-jne2 mb95f562kpft-g-jne2 mb95f563hpft-g-jne2 mb95f563kpft-g-jne2 mb95f564hpft-g-jne2 mb95f564kpft-g-jne2 20-pin plastic tssop (fpt-20p-m10) mb95f582hwqn-g-jne1 mb95f582hwqn-g-jnere1 mb95f582kwqn-g-jne1 mb95f582kwqn-g-jnere1 mb95f583hwqn-g-jne1 MB95F583HWQN-G-JNERE1 mb95f583kwqn-g-jne1 mb95f583kwqn-g-jnere1 mb95f584hwqn-g-jne1 mb95f584hwqn-g-jnere1 mb95f584kwqn-g-jne1 mb95f584kwqn-g-jnere1 32-pin plastic qfn (lcc-32p-m19) mb95f582hpft-g-jne2 mb95f582kpft-g-jne2 mb95f583hpft-g-jne2 mb95f583kpft-g-jne2 mb95f584hpft-g-jne2 mb95f584kpft-g-jne2 16-pin plastic tssop (fpt-16p-m08) mb95f582hpf-g-jne2 mb95f582kpf-g-jne2 mb95f583hpf-g-jne2 mb95f583kpf-g-jne2 mb95f584hpf-g-jne2 mb95f584kpf-g-jne2 16-pin plastic sop (fpt-16p-m23) mb95f572hpf-g-jne2 mb95f572kpf-g-jne2 mb95f573hpf-g-jne2 mb95f573kpf-g-jne2 mb95f574hpf-g-jne2 mb95f574kpf-g-jne2 8-pin plastic sop (fpt-8p-m08)
mb95560h/570h/580h series ds702-00003-1v0-e 77 package dimension please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 32-pin plastic qfn lead pitch 0.50 mm package width package length 5.00 mm 5.00 mm sealing method plastic mold mounting height 0.80 mm max weight 0.06 g 32-pin plastic qfn (lcc-32p-m19) (lcc-32p-m19) (.010 ) c 2009-2010 fujitsu semiconductor limited c32071s-c-1-2 (.197 .004) 5.00 0.10 5.00 0.10 (.197 .004) (3-r0.20) ((3-r.008)) 0.50(.020) 1pin corner (c0.30(c.012)) 0.75 0.05 (0.20(.008)) index area 0.40 0.05 (.016 .002) +0.03 ? 0.02 ? .001 +.001 0.02 (.001 ) (.138 .004) 3.50 0.10 3.50 0.10 (.138 .004) (typ) (.030 .002) +0.05 ? 0.07 ? .003 +.002 0.25 dimensions in mm (inches). note: the values in parentheses are reference values.
mb95560h/570h/580h series 78 ds702-00003-1v0-e please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 20-pin plastic sop lead pitch 1.27 mm package width package length 7.50 mm 12.70 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 2.65 mm max 20-pin plastic sop (fpt-20p-m09) (fpt-20p-m09) c 2008-2010 fujitsu semiconductor limited f20030s-c-1-2 details of "a" part index 0.10(.004) (.008 .004) 0.20 0.10 ? .007 +.005 .099 ? 0.17 +0.13 2.52 (mounting height) 0~8 (stand off) 0.80 +0.47 ? 0.30 .031 +.019 ? .012 "a" ? .001 +.003 .010 0.25 +0.07 ? 0.02 #12.70 0.10(.500 .004) 11 20 1.27(.050) 1 10 0.25(.010) m ? 0.05 +0.09 0.40 .016 +.004 ? .002 #7.50 0.10 (.295 .004) ? 0.20 +0.40 10.2 .402 +.016 ? .008 btm e-mark dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness. note 2) pins width do not include tie bar cutting remainder. note 3) # : these dimensions do not include resin protrusion.
mb95560h/570h/580h series ds702-00003-1v0-e 79 please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 20-pin plastic tssop lead pitch 0.65 mm package width package length 4.40 mm 6.50 mm lead shape gullwing sealing method plastic mold mounting height 1.20 mm max weight 0.08 g 20-pin plastic tssop (fpt-20p-m10) (fpt-20p-m10) c 2009-2010 fujitsu semiconductor limited f20031s-c-1-2 #6.50 0.10(.256 .004) #4.40 0.10 6.40 0.20 (.252 .008) (.173 .004) 0.10(.004) 0.65(.026) 0.24 0.04 (.009 .002) 1 10 20 11 "a" details of "a" part 0~8 (.024 .006) 0.60 0.15 max 1.20(.047) (mounting height) 0.10 0.05 (stand off) lead no. index btm e-mark (.004 .002) 0.14 +0.05 ?0.04 +.002 ?.002 .006 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness. note 2) pins width do not include tie bar cutting remainder. note 3) # : these dimensions do not include resin protrusion.
mb95560h/570h/580h series 80 ds702-00003-1v0-e please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 16-pin plastic tssop lead pitch 0.65 mm package width package length 4.40 mm 4.96 mm lead shape gullwing sealing method plastic mold mounting height 1.20 mm max weight 0.06 g 16-pin plastic tssop (fpt-16p-m08) (fpt-16p-m08) c 2007-2010 fujitsu semiconductor limited f16021s-c-1-5 *4.96 0.10(.195 .004) *4.40 0.10 6.40 0.20 (.252 .008) (.173 .004) 0.10(.004) 0.65(.026) 0.24 0.08 (.009 .003) 1 8 16 9 "a" 0.145 0.045 (.0057 .0018) m 0.13(.005) details of "a" part 0~8 (.024 .006) 0.60 0.15 0.10 0.05 (stand off) lead no. index .043 1.10 (mounting height) (.004 .002) +0.04 ?0.06 +0.10 ?0.15 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness. note 2) pins width do not include tie bar cutting remainder. note 3) * : these dimensions do not include resin protrusion.
mb95560h/570h/580h series ds702-00003-1v0-e 81 please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 16-pin pl as tic s op le a d pitch 1.27 mm p a ck a ge width p a ck a ge length 3 .90 mm 9.96 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.75 mm max weight 0.12 g 16-pin pl as tic s op (fpt-16p-m2 3 ) (fpt-16p-m2 3 ) c 2010 fujit s u s emiconductor limited hm b f16-2 3s c-1-1 #9.96 0.10(. 3 92 .004) # 3 .90 0.10 6.00 0.20 (.2 3 6 .00 8 ) (.154 .004) 0.10(.004) 1.27(.050) 0.40 (.016 ) 1 16 m 0.25(.010) 7 index .024 0.60 +0.0 8 ?0.06 +0.20 ?0.15 8 9 btm e-mark +0.11 ?0.04 +.004 ?.002 (.026 .004) 0.65 0.10 .006 0.15 +0.04 ?0.02 +0.10 ?0.05 (.057 .00 8 ) 1.45 0.20 .06 3 1.60 +0.06 ?0.10 +0.15 ?0.25 2 7 2 8 2 (.016 .004) 0.40 0.10 (.016 .004) 0.40 0.10 8 2 (1.04 (.041)) dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 2) pin s width do not incl u de tie ba r c u tting rem a inder. note 3 ) #: the s e dimen s ion s do not incl u de re s in protr us ion.
mb95560h/570h/580h series 82 ds702-00003-1v0-e (continued) please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 8-pin plastic sop lead pitch 1.27 mm package width package length 5.30 mm 5.24 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 2.10 mm max 8-pin plastic sop (fpt-8p-m08) (fpt-8p-m08) c 2008-2010 fujitsu semiconductor limited f08016s-c-1-2 details of "a" part #5.30 0.10 (.209 .004) index 1.27(.050) 1 4 5 8 0.43 0.05 (.017 .002) "a" (stand off) 0~8 (mounting height) 2.10(.083) max 0.10 +0.15 ? 0.05 ? .002 +.006 .004 7.80 +0.45 ? 0.10 +.018 ? .004 .307 #5.24 0.10 (.206 .004) btm e-mark 0.20 0.05 (.008 .002) +0.10 ? 0.20 0.75 .030 +.004 ? .008 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness. note 2) pins width do not include tie bar cutting remainder. note 3) # : these dimensions do not include resin protrusion.
mb95560h/570h/580h series ds702-00003-1v0-e 83 memo
mb95560h/570h/580h series fujitsu semiconductor limited nomura fudosan shin-yokohama bldg. 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fujitsu.com/sg/se rvices/micro/semiconductor/ fujitsu semiconductor shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ specifications are subject to change without notice. for further inform ation please cont act each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this docu ment are presented solely for t he purpose of reference to show examples of op erations and uses of fuji tsu semiconductor device; fujitsu semiconductor does not warrant proper operation of th e device with respect to use based on such information. when you develop equipment incorporat ing the device based on such inform ation, you must assume any res ponsibility arising out of su ch use of the information. fujitsu semicond uctor assumes no liability for any damages whatsoev er arising out of the use of the information. any information in this document, including descriptions of func tion and schematic diagrams, sha ll not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyrig ht, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconduc tor assumes no liability for any infringe ment of the intellec tual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household us e, but are not designed, developed and m anufactured as contemplated (1) for use accomp anying fatal risks or dangers th at, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requirin g extremely high reliability (i.e., submer sible repeater and artificial satellite). please note that fujits u semiconductor will not be liable ag ainst you and/or any third party for any claims or damages aris- ing in connection with above-m entioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety de sign measures into your facility a nd equipment such as redundancy, fire protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade contro l law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

▲Up To Search▲

Price & Availability of MB95F583HWQN-G-JNERE1

	To Download MB95F583HWQN-G-JNERE1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .